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5.9 Switching Characteristics—Serial Control Port–SPI Slave Mode
Internal DCLK period 1
Parameter
CS4852x-CQZ
CS4854x-CQZ
CS4856x-CQZ
CS4854x-DQZ
CS4856x-DQZ
Symbol
DCLKP
Min
—
6.7
6.7
6.7
6.7
6.7
Max
—
1/F xtal
1/F xtal
1/F xtal
1/F xtal
1/F xtal
Unit
ns
1.After initial power-on reset, F dclk = F xtal . After initial kick-start commands, the PLL is locked to max F dclk and remains locked until the next power-on
reset.
5.9 Switching Characteristics—Serial Control Port–SPI Slave Mode
Parameter
SCP_CLK frequency 1
SCP_CS# falling to SCP_CLK rising
SCP_CLK low time
SCP_CLK high time
Setup time SCP_MOSI input
Hold time SCP_MOSI input
SCP_CLK low to SCP_MISO output valid
SCP_CLK falling to SCP_IRQ# rising
SCP_CS# rising to SCP_IRQ# falling
SCP_CLK low to SCP_CS# rising
SCP_CS# rising to SCP_MISO output high-Z
SCP_CLK rising to SCP_BSY# falling
Symbol
f spisck
t spicss
t spickl
t spickh
t spidsu
t spidh
t spidov
t spiirqh
t spiirql
t spicsh
t spicsdz
t spicbsyl
Min
—
24
20
20
5
5
—
—
0
24
—
—
Typical
—
—
—
—
—
—
—
—
—
—
20
3*DCLKP+20
Max
25
—
—
—
—
—
11
20
—
—
—
—
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.The specification f spisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the
communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of
the input data buffer. At boot the maximum speed is F xtal /3.
t spicss
SCP_CS#
0
1
2
t spickl
6
7
0
5
6
7
t spicsh
SCP_CLK
f spisck
t spickh
SCP_MOSI
A6
A5
A0
R/W
MSB
LSB
t spidsu
SCP_MISO
t spidh
t spidov
MSB
t spiirqh
LSB
t spicsdz
t spiirql
SCP_IRQ#
t spibsyl
SCP_BSY#
Figure 5-3. Serial Control Port–SPI Slave Mode Timing
12
DS734F5
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